ECAD Pages	Search WWW Search www.bychoice.com   Don't miss important Freeware on this Page
Got Ferret32? If not your working too hard!   Click here.   To go to Ferret32's website or Icon button below. Windows is greatly augmented with Ferret32. Find out more ?

Dilbert Today

• S Parameter File Viewer form LeCroy
• Net Finder Cadence Utility TL2
• Cadence_Device_check_GUI Utility
• Cadence DML Status
• checklistManager (Visual Basic)
  EDIF (Electronic Design Interchange Format)
  
• EDIF Translators
• EDIF 2, 3 ,& 4 RSI CADCAM
• EPD Add Differential Pairs for Allegro to DxDesigner Schematics Utility for Mentor Graphics (Visual Basic)
• Freeware Utilities at Bychoice.com
• InterComm™ Design Automation
• Part Libarian Utility for Mentor Graphics (Visual Basic)
• Reference EPD 3.0 DxDesigner Viewdraw File Format (Mentor Graphics ) (text)
• Router Solutions Releases CAMCAD Version 4.3.0
• Vendors ECAD Assorted Software Program Links
• Lattice Semiconductor
• Native VIEWERS

Terms of Use:

WARRANTY-DISCLAIMER OF WARRANTY The Owner (provider) expressly disclaims all warranties, including the implied warranties of merchantability, fitness for a particular purpose, and non-infringement. The Site, Documentation, and Download are provided on an "as is" basis. The Owner does not warrant that the Site, Documentation, and Download will suit your purposes; nor that they are free of all defects; nor that any defects will be corrected. If the Site, Documentation, or Download is defective, You agree to assume all costs associated with servicing, repair, or correction that You require. You agree that this disclaimer is an essential part of the License to use said software or documents. You can not use the Site except under this disclaimer.

LIMITATIONS OF LIABILITY The Owner (provider) shall not be liable under any circumstances or legal theory, whether contract, tort, or otherwise, for consequential, indirect, incidental, special, or exemplary damages, including lost data or profits, arising out of this License or your use of the Site, Documentation, or Download, even if the Owner has been advised of the possibility of such damages or some remedy set forth herein has failed in its purpose.

(top)  (Home)

CheckList Manager

This program is a productivity tool design to make managing checklists, their import, signoff, and proofing easier than convential office approaches. The program is self contained and comes with an installation program for Microsoft operating platforms WIN XP and WIN 2000.

Refer to screen shot of the Checklist Manager.

The database is maintained in a comma delimited file format (.csv) that both are native to the Checklist Manager and Microsoft Excel. See sample checklist file.

To speed up the signoff process, three standard responses are coded into the database. The current status is changed to one of these by simply clicking "CHANGE".

A comment field is also maintained for notes and comments.

Color is used to easiliy identify a checklist for which status is pending, whereas, white indicates status has been assigned.

Info on this program in PDF is contained once installed.

Net Finder Cadence Utility TL2

This program extracts a spreadsheet of nets of a device from the Cadence Allegro TL2 Netlist. This is useful for checking or programming FPGA pin assignments. This is freeware from Lockheed IS&S in San Jose

Cadence DML Status

Keeps track of a Library of Ibis and DML files, reporting revision, manufactures, revision history, part numbers, warning, and errors. Makes the simulation library process manageable.

Cadence_Device_check_GUI Utility

Automates the running of the batch command that compares device files and package symbol definitions and generates a log file listing any discrepancies.

• Checks the syntax of the device files specified in the command.
• Creates a temporary netlist called dev_check.net, which consists of the $PACKAGES section of the netlist file. The dev_check.net file contains no information and is used only to check symbols against the device files. The $PACKAGES file section creates U1, U2, U3 and so on, sequentially. The dev_check command creates a temporary drawing called dev_check.brd and runs the netin command, which loads a $PACKAGES section of a netlist into the drawing so that Allegro/APD can check the devices and symbols in the drawing.
• Creates a dev_check.log file which contains a netin.log.

This GUI:

• Identifies any errors as listed in the netin.log and displays them on the screen.
• Provide a list of all parts (text files) to check in the directory selected
• Conviently allow the user to select what to check,

The Cadence Perl script dev_check.pl has a -r option that is obsolete. Edit it out of the file. See above PDF for more about this. (Path usually is something like this: C:\Cadence\SPB_15.2\tools\pcb\bin). To download an edited version for SPB v15.2 click here.

(top)  (Home)

EPD Add Differential Pairs for Allegro to DxDesigner Schematics

(top)  (Home)

Mentor Graphics EPD DxDesigner Part Librarian Utility (visual basic)

(top)  (Home)

VIEWERS

• S Parameter File Viewer form LeCroy
• Viewers ( Gerber, DWG, DWX, VRML, IGES, STL,

HPGL, CGM, GIF, BMP, Targa, JPEG, PNG files)

(top)  (Home)

Lattice Semiconductor

Links:

• ispLEVER Starter is a downloadable version of ispLEVER for Windows
• LatticeXP FPGA devices utilize a combination of non-volatile FLASH cells and SRAM technology
• Lattice Devices   Software Download

SCHEMATICS

Turning On Attribute Slow Rise time

Lattice schematic entry Making an IO Cell Registered (1000 series devices)

(top)  (Home)

(top)  (Home)